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#1 2018-02-21 09:21:56

iceman
Administrator
Registered: 2013-04-25
Posts: 4,854
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SPI on AT91SAM7S512 (MCU)

The PM3 Evo device has a flashmemory on  GPIO_PA10,  which is SPI muxed to Peripheral B,  as NPCS2.
However the SPI don't want to talk with it.  I must be making some mistake. 
https://github.com/iceman1001/proxmark3 … hmem.c#L39

This is the SPI setup for it.

/* here: use NCPS2 @ PA10: */
#define NCPS_PDR_BIT     AT91C_PA10_NPCS2	// GPIO
#define NCPS_ASR_BIT     0					// SPI peripheral A
#define NCPS_BSR_BIT     AT91C_PA10_NPCS2	// SPI peripheral B
#define SPI_CSR_NUM      2          		// Chip Select register[] 0,1,2,3  (at91samv512 has 4)

/* PCS_0 for NPCS0, PCS_1 for NPCS1 ... */
#define PCS_0  ((0<<0)|(1<<1)|(1<<2)|(1<<3)) // 0xE - 1110
#define PCS_1  ((1<<0)|(0<<1)|(1<<2)|(1<<3)) // 0xD - 1101
#define PCS_2  ((1<<0)|(1<<1)|(0<<2)|(1<<3)) // 0xB - 1011
#define PCS_3  ((1<<0)|(1<<1)|(1<<2)|(0<<3)) // 0x7 - 0111

/* TODO: ## */
#if (SPI_CSR_NUM == 0)
#define SPI_MR_PCS       PCS_0
#elif (SPI_CSR_NUM == 1)
#define SPI_MR_PCS       PCS_1
#elif (SPI_CSR_NUM == 2)
#define SPI_MR_PCS       PCS_2
#elif (SPI_CSR_NUM == 3)
#define SPI_MR_PCS       PCS_3
#else
#error "SPI_CSR_NUM invalid"
// not realy - when using an external address decoder...
// but this code takes over the complete SPI-interace anyway
#endif
/*
1.  variable chip select (PS=1)  ChipSelect number is written to TDR in EVERY transfer
2.  fixed chip select (PS=0), 

FIXED 		= you manage the CS lines
VARIABLE 	= SPI module manages the CS lines
*/

void FlashSetup(void) {
	// PA1	-> SPI_NCS3 chip select (MEM)
	// PA12 -> SPI_MISO Master-In Slave-Out
	// PA13 -> SPI_MOSI Master-Out Slave-In
	// PA14 -> SPI_SPCK Serial Clock

	// Kill all the pullups,
	//AT91C_BASE_PIOA->PIO_PPUDR = NCPS_PDR_BIT | GPIO_MOSI | GPIO_SPCK | GPIO_MISO;

	// These pins are outputs
	//AT91C_BASE_PIOA->PIO_OER = NCPS_PDR_BIT | GPIO_MOSI | GPIO_SPCK;

	// PIO controls the following pins
	//AT91C_BASE_PIOA->PIO_PER = NCPS_PDR_BIT | GPIO_MOSI | GPIO_SPCK | GPIO_MISO;

	// Disable PIO control of the following pins, hand over to SPI control
	AT91C_BASE_PIOA->PIO_PDR = GPIO_MISO | GPIO_MOSI | GPIO_SPCK | NCPS_PDR_BIT;
		
	// Peripheral A
	AT91C_BASE_PIOA->PIO_ASR = GPIO_MISO | GPIO_MOSI | GPIO_SPCK | NCPS_ASR_BIT;
	// Peripheral B
	AT91C_BASE_PIOA->PIO_BSR = GPIO_MISO | GPIO_MOSI | GPIO_SPCK | NCPS_BSR_BIT ;

	// set chip-select as output high (unselect card)
	AT91C_BASE_PIOA->PIO_PER  = NCPS_PDR_BIT; // enable GPIO of CS-pin
	AT91C_BASE_PIOA->PIO_SODR = NCPS_PDR_BIT; // set high
	AT91C_BASE_PIOA->PIO_OER  = NCPS_PDR_BIT; // output enable
	
	//enable the SPI Peripheral clock
	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI);

	// Enable SPI
	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
	
	// SPI Mode register
	/*
	AT91C_BASE_SPI->SPI_MR =
		(0 << 24)			|	// DLYBCS, Delay between chip selects (take default: 6 MCK periods)
		(0 << 7)			|	// LLB, Local Loopback Disabled
		AT91C_SPI_MODFDIS	|	// Mode Fault Detection disabled
		(0 << 2)			|	// PCSDEC, Chip selects connected directly to peripheral
		AT91C_SPI_PS_FIXED	|	// PS, Fixed Peripheral Select
		AT91C_SPI_MSTR;			// MSTR, Master Mode
		*/
	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR  | AT91C_SPI_PS_FIXED | AT91C_SPI_MODFDIS;
		
	// PCS, Peripheral Chip Select
	AT91C_BASE_SPI->SPI_MR |= ( (SPI_MR_PCS << 16) & AT91C_SPI_PCS );

	// SPI Chip select register
	AT91C_BASE_SPI->SPI_CSR[SPI_CSR_NUM] =
		(1 << 24)			|	// Delay between Consecutive Transfers (32 MCK periods)
		(1 << 16) 			|	// Delay Before SPCK (1 MCK period)
		(6 << 8) 			|	// Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
		AT91C_SPI_BITS_8	|	// Bits per Transfer (8 bits)
		(0 << 3) 			|	// CSAAT, Chip Select inactive after transfer
		AT91C_SPI_NCPHA		|	// NCPHA, Clock Phase data captured on leading edge, changes on following edge
		(0 << 0);				// CPOL, Clock Polarity inactive state is logic 0

	//AT91C_BASE_SPI->SPI_CSR[SPI_CSR_NUM] =  AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 | (6 << 8);
	
		/* Send 20 spi commands with card not selected */
	for (int i=0; i<21; i++)
		FlashSend(0xFF);

	
	/* enable automatic chip-select */
	/*
	// reset PIO-registers of CS-pin to default
	AT91C_BASE_PIOA->PIO_ODR  |= NCPS_PDR_BIT; // input
	AT91C_BASE_PIOA->PIO_CODR |= NCPS_PDR_BIT; // clear
	// disable PIO from controlling the CS pin (=hand over to SPI)
	AT91C_BASE_PIOA->PIO_PDR |= NCPS_PDR_BIT;
	// set pin-functions in PIO Controller (function NCPS for CS-pin)
	AT91C_BASE_PIOA->PIO_ASR |= NCPS_ASR_BIT;
	AT91C_BASE_PIOA->PIO_BSR |= NCPS_BSR_BIT;
	*/
}

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